Austrochip 2016

24th Austrian Workshop on Microelectronics
October 19th, 2016 - Villach, Austria

ISCD - Integrated Systems and Circuits Design.

Austrochip 2016 Conference Program:

08:00 - 09:00 Registration and Breakfast
09:00 - 09:15 Conference Opening
09:15 - 10:15 Keynote Address
  • Analog and Digital Signal Processing Electronics for Multi-channel, High Sensitivity Vapor Trace Detection System
    Drago Strle
10:15 - 10:45 Coffee Break, Exhibition, Poster
10:45 - 12:15 Session I: Analog and Power Management
  • Advanced Pseudo Differential Amplifier with Output Common Mode Regulation and Phase Shift Retention.
    Sagarika Donepudi, Michael Köberle and Wolfgang Horn
  • Modeling and Simulation of Digital Control Schemes for Two-Phase Interleaved Buck Converters.
    Marc Kanzian, Matteo Agostinelli and Mario Huemer
  • High-Efficiency CMOS Buck Converter with Wide Output Voltage Range
    Natasa Mitrovic, Reinhard Enne and Horst Zimmermann.
  • A 11-bit Integrating Analog to Digital Converter
    Darshan Shetty and Pratap Tumkur Renukaswamy.
12:15 - 14:00 Lunch, Exhibition, Poster
14:00 - 15:30 Session II: RF and Analog
  • Analysis and Design of Differential Feedback CG LNA Topologies for Low Voltage Multistandard Wireless Receivers.
    Pratap Tumkur Renukaswamy, Vijaya Sankara Rao Pasupureddi and Johannes Sturm
  • Threshold Voltage Compensated RF-DC Power Converters in a 40 nm CMOS Technology.
    Lukas Zöscher, Peter Herkess, Jasmin Grosinger, Ulrich Muehlmann, Dominik Amschl, Hubert Watzinger and Wolfgang Bösch.
  • System-in-Package Matching Network for RF Wireless Transceivers
    Graciele Batistell, Timo Holzmann, Hermann Sterner and Johannes Sturm.
  • A Capacity-to-Digital Converter Based on a Ring Oscillator with Flicker Noise Reduction
    Andres Quintero Alonso, Fernando Cardes Garcia, Luis Hernandez Corporales, Cesare Buffa and Andreas Wiesbauer.
15:30 - 16:00 Coffee Break, Exhibition, Poster
16:00 - 17:10 Session III: Embedded Systems and Digital
  • On Analysis of Software Interrupt Limiters for Embedded Systems by Means of UPPAAL SMC.
    Josef Strnadel and Michal Risa
  • A Programmable Delay Line for Metastability Characterization in FPGAs.
    Thomas Polzer, Florian Huemer and Andreas Steininger.
  • An EMI Receiver Model to Minimize Simulation Time of Long Data Transmissions
    Herbert Hackl, Bernd Deutschmann.
17:10 - 17:20 Outlook Austrochip 2017

ARGE HFT Program:

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